EDA tools support the addition of MBIST logic to an IC design to add testability of memory to the IC design. Traditionally, the EDA design flow and associated EDA tools have focused on adding an MBIST logic immediately before the memory under test.
However, the memory under test is commonly part of a larger module with intervening circuitry in between the ports of the larger module and the memory under test. Traditional approaches modify the larger module itself by adding the MBIST logic within the larger module, after the intervening circuitry and immediately before the memory under test. Such approaches fail to test the integration of the memory within the larger module.
Also, when the larger module is intellectual property (IP) from a vendor, the vendor may not guarantee performance of the IP upon such modification of the IP. Accordingly, an EDA user is faced with the quandary of either not adding MBIST logic to the IP, or adding the MBIST logic and losing the backing of the IP vendor behind any guaranteed performance of the IP.
Traditionally, different or multiple MBIST logic may be required to test different variations of the memories.